feat(hal): add multiple register definitions (SYSCFG, XSPI, SID, SPI ENC, RTC)

artinchip-hal/src/gtc/register.rs

@@ -166,7 +166,7 @@ impl Config {
     #[inline]
     pub const fn set_fdiv(self, div: u16) -> Self {
         assert!(
-            div <= 0x1F,
+            div < 0x20,
             "Frequency divider out of range (expected 0..=31)"
         );
         Self((self.0 & !Self::FDIV) | (Self::FDIV & ((div as u32) << 8)))

artinchip-hal/src/i2c/register.rs

@@ -1394,7 +1394,7 @@ impl RxThreshold {
     #[doc(alias = "RX_TL")]
     #[inline]
     pub const fn set_rx_threshold(self, thres: u8) -> Self {
-        assert!(thres < 8, "Threshold out of range (expected 0..=8)");
+        assert!(thres < 8, "Threshold out of range (expected 0..=7)");
         Self((self.0 & !Self::RX_TL) | ((thres as u32) & Self::RX_TL))
     }
     /// Get rx threshold.
@@ -1416,7 +1416,7 @@ impl TxThreshold {
     #[doc(alias = "TX_TL")]
     #[inline]
     pub const fn set_tx_threshold(self, thres: u8) -> Self {
-        assert!(thres < 8, "Threshold out of range (expected 0..=8)");
+        assert!(thres < 8, "Threshold out of range (expected 0..=7)");
         Self((self.0 & !Self::TX_TL) | ((thres as u32) & Self::TX_TL))
     }
     /// Get tx threshold.
@@ -1732,7 +1732,9 @@ mod tests {
 
     #[test]
     fn struct_interrupt_mask_functions() {
-        let mut val = InterruptMask(0x0);
+        let mut val = InterruptMask(0x1234_5678);
+        val = val.disable_all();
+        assert_eq!(val.0, 0x0000_0000);
 
         val = val.enable_scl_stuck_at_low();
         assert!(val.is_scl_stuck_at_low_enabled());
@@ -2041,7 +2043,7 @@ mod tests {
     test_should_panic!((
         test_set_rx_threshold_panic,
         RxThreshold(0x0).set_rx_threshold(0x8),
-        "Threshold out of range (expected 0..=8)"
+        "Threshold out of range (expected 0..=7)"
     ),);
 
     #[test]
@@ -2055,7 +2057,7 @@ mod tests {
     test_should_panic!((
         test_set_tx_threshold_panic,
         TxThreshold(0x0).set_tx_threshold(0x8),
-        "Threshold out of range (expected 0..=8)"
+        "Threshold out of range (expected 0..=7)"
     ),);
 
     #[test]

artinchip-hal/src/lib.rs

@@ -9,9 +9,14 @@ pub mod gpio;
 pub mod gtc;
 pub mod i2c;
 pub mod qspi;
+pub mod rtc;
 pub mod sdmc;
+pub mod sid;
+pub mod spi_enc;
+pub mod sys_cfg;
 pub mod uart;
 pub mod wri;
+pub mod xspi;
 
 mod macros;
 

artinchip-hal/src/qspi/register.rs

@@ -1,5 +1,6 @@
 //! QSPI register blocks and registers.
 
+use embedded_hal::spi::{Phase, Polarity};
 use volatile_register::{RO, RW, WO};
 
 /// Quad Serial Peripheral Interface Register Block.
@@ -292,36 +293,6 @@ pub enum CsValidMode {
     InactiveWhenIdle,
 }
 
-/// CS polarity.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-#[repr(u8)]
-pub enum CsPolarity {
-    /// Valid when CS is low.
-    Low,
-    /// Valid when CS is high.
-    High,
-}
-
-/// Clock polarity.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-#[repr(u8)]
-pub enum ClockPolarity {
-    /// Clock is low when idle.
-    Low,
-    /// Clock is high when idle.
-    High,
-}
-
-/// Clock phase.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-#[repr(u8)]
-pub enum ClockPhase {
-    /// Data sampled on the first edge of the clock.
-    FirstEdge,
-    /// Data sampled on the second edge of the clock.
-    SecondEdge,
-}
-
 /// SPI transfer configuration register.
 #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
 #[repr(transparent)]
@@ -602,15 +573,15 @@ impl TransferConfig {
     /// Not writable when `START` = 1.
     #[doc(alias = "CS_POL")]
     #[inline]
-    pub const fn set_cs_pol(self, pol: CsPolarity) -> Self {
+    pub const fn set_cs_pol(self, pol: Polarity) -> Self {
         Self((self.0 & !Self::CS_POL) | (Self::CS_POL & ((pol as u32) << 2)))
     }
     /// Get cs polarity.
     #[inline]
-    pub const fn cs_pol(self) -> CsPolarity {
+    pub const fn cs_pol(self) -> Polarity {
         match (self.0 & Self::CS_POL) >> 2 {
-            0 => CsPolarity::Low,
-            1 => CsPolarity::High,
+            0 => Polarity::IdleLow,
+            1 => Polarity::IdleHigh,
             _ => unreachable!(),
         }
     }
@@ -619,15 +590,15 @@ impl TransferConfig {
     /// Not writable when `START` = 1.
     #[doc(alias = "CPOL")]
     #[inline]
-    pub const fn set_clk_pol(self, pol: ClockPolarity) -> Self {
+    pub const fn set_clk_pol(self, pol: Polarity) -> Self {
         Self((self.0 & !Self::CPOL) | (Self::CPOL & ((pol as u32) << 1)))
     }
     /// Get clock polarity.
     #[inline]
-    pub const fn clk_pol(self) -> ClockPolarity {
+    pub const fn clk_pol(self) -> Polarity {
         match (self.0 & Self::CPOL) >> 1 {
-            0 => ClockPolarity::Low,
-            1 => ClockPolarity::High,
+            0 => Polarity::IdleLow,
+            1 => Polarity::IdleHigh,
             _ => unreachable!(),
         }
     }
@@ -636,15 +607,15 @@ impl TransferConfig {
     /// Not writable when `START` = 1.
     #[doc(alias = "CPHA")]
     #[inline]
-    pub const fn set_clk_phase(self, phase: ClockPhase) -> Self {
-        Self((self.0 & !Self::CPHA) | (Self::CPHA & (phase as u32)))
+    pub const fn set_clk_pha(self, pha: Phase) -> Self {
+        Self((self.0 & !Self::CPHA) | (Self::CPHA & (pha as u32)))
     }
     /// Get clock phase.
     #[inline]
-    pub const fn clk_phase(self) -> ClockPhase {
+    pub const fn clk_pha(self) -> Phase {
         match self.0 & Self::CPHA {
-            0 => ClockPhase::FirstEdge,
-            1 => ClockPhase::SecondEdge,
+            0 => Phase::CaptureOnFirstTransition,
+            1 => Phase::CaptureOnSecondTransition,
             _ => unreachable!(),
         }
     }
@@ -1431,7 +1402,7 @@ impl ClkConfig {
     #[doc(alias = "CKDIV1")]
     #[inline]
     pub const fn set_clk_div_1(self, div: u8) -> Self {
-        assert!(div <= 0xF, "CKDIV1 out of range (expected 0..=15)");
+        assert!(div < 0x10, "CKDIV1 out of range (expected 0..=15)");
         Self((self.0 & !Self::CKDIV1) | (Self::CKDIV1 & ((div as u32) << 8)))
     }
     /// Get clock divider 1.
@@ -1467,7 +1438,7 @@ impl TotalBytesCnt {
     #[inline]
     pub const fn set_total_bytes(self, bytes: u32) -> Self {
         assert!(
-            bytes <= 0xFFFFFF,
+            bytes < 0x1000000,
             "Total bytes out of range (expected 0..=0xFFFFFF)"
         );
         Self((self.0 & !Self::TOTAL_BYTES) | (Self::TOTAL_BYTES & bytes))
@@ -1492,7 +1463,7 @@ impl TransCnt {
     #[inline]
     pub const fn set_tx_cnt(self, cnt: u32) -> Self {
         assert!(
-            cnt <= 0xFFFFFF,
+            cnt < 0x1000000,
             "Transmit write counter out of range (expected 0..=0xFFFFFF)"
         );
         Self((self.0 & !Self::TXD_CNT) | (Self::TXD_CNT & cnt))
@@ -1612,7 +1583,7 @@ impl TransMiscControl {
     #[inline]
     pub const fn set_single_tx_count(self, count: u32) -> Self {
         assert!(
-            count <= 0xFFFFFF,
+            count < 0x1000000,
             "Single wire tx data count out of range (expected 0..=0xFFFFFF)"
         );
         Self((self.0 & !Self::STXD_CNT) | (Self::STXD_CNT & count))
@@ -1658,16 +1629,6 @@ pub enum BMCsPin {
     Cs0,
 }
 
-/// Bit-mode CS polarity.
-#[derive(Clone, Copy, Debug, PartialEq, Eq)]
-#[repr(u8)]
-pub enum BMCsPolarity {
-    /// Valid when CS is high.
-    High,
-    /// Valid when CS is low.
-    Low,
-}
-
 /// Bus mode.
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]
 #[repr(u8)]
@@ -1768,7 +1729,7 @@ impl BitModeTransConfig {
     #[inline]
     pub const fn set_bm_rx_count(self, count: u8) -> Self {
         assert!(
-            count <= 0x3F,
+            count < 0x40,
             "Bit-mode rx data length out of range (expected 0..=63)"
         );
         Self((self.0 & !Self::BM_RXCNT) | (Self::BM_RXCNT & ((count as u32) << 16)))
@@ -1786,7 +1747,7 @@ impl BitModeTransConfig {
     #[inline]
     pub const fn set_bm_tx_count(self, count: u8) -> Self {
         assert!(
-            count <= 0x3F,
+            count < 0x40,
             "Bit-mode tx count out of range (expected 0..=63)"
         );
         Self((self.0 & !Self::BM_TXCNT) | (Self::BM_TXCNT & ((count as u32) << 8)))
@@ -1838,15 +1799,15 @@ impl BitModeTransConfig {
     /// Not writable when `BM_START` = 1.
     #[doc(alias = "BMCS_POL")]
     #[inline]
-    pub const fn set_bm_cs_polarity(self, polarity: BMCsPolarity) -> Self {
-        Self((self.0 & !Self::BMCS_POL) | (Self::BMCS_POL & ((polarity as u32) << 5)))
+    pub const fn set_bm_cs_pol(self, pol: Polarity) -> Self {
+        Self((self.0 & !Self::BMCS_POL) | (Self::BMCS_POL & ((pol as u32) << 5)))
     }
     /// Get bit-mode cs polarity.
     #[inline]
-    pub const fn bm_cs_polarity(self) -> BMCsPolarity {
+    pub const fn bm_cs_pol(self) -> Polarity {
         match (self.0 & Self::BMCS_POL) >> 5 {
-            0 => BMCsPolarity::High,
-            1 => BMCsPolarity::Low,
+            0 => Polarity::IdleLow,
+            1 => Polarity::IdleHigh,
             _ => unreachable!(),
         }
     }
@@ -1949,7 +1910,7 @@ impl BurstSet {
     #[inline]
     pub fn set_dummy_byte_cnt(self, count: u8) -> Self {
         assert!(
-            count <= 0xF,
+            count < 0x10,
             "Dummy byte count out of range (expected 0..=15)"
         );
         Self((self.0 & !Self::DUMMY_BYTE) | (Self::DUMMY_BYTE & ((count as u32) << 20)))
@@ -2062,7 +2023,7 @@ impl ReadCmdMode {
     #[inline]
     pub const fn set_dummy_byte_cnt(self, count: u8) -> Self {
         assert!(
-            count <= 0xF,
+            count < 0x10,
             "Dummy byte count out of range (expected 0..=15)"
         );
         Self((self.0 & !Self::DUMMY_BYTE) | (Self::DUMMY_BYTE & ((count as u32) << 20)))
@@ -2218,7 +2179,7 @@ impl IdmaTxLen {
     #[inline]
     pub const fn set_idma_tx_len(self, len: u32) -> Self {
         assert!(
-            len <= 0xFFFFFF,
+            len < 0x1000000,
             "IDMA tx length out of range (expected 0..=0xFFFFFF)"
         );
         Self((self.0 & !Self::IDMA_TXLEN) | (Self::IDMA_TXLEN & len))
@@ -2243,7 +2204,7 @@ impl IdmaRxLen {
     #[inline]
     pub const fn set_idma_rx_len(self, len: u32) -> Self {
         assert!(
-            len <= 0xFFFFFF,
+            len < 0x1000000,
             "IDMA rx length out of range (expected 0..=0xFFFFFF)"
         );
         Self((self.0 & !Self::IDMA_RXLEN) | (Self::IDMA_RXLEN & len))
@@ -2552,25 +2513,25 @@ mod tests {
         assert_eq!(val.cs_valid_mode(), CsValidMode::Continuous);
         assert_eq!(val.0, 0x0000_0000);
 
-        val = val.set_cs_pol(CsPolarity::High);
-        assert_eq!(val.cs_pol(), CsPolarity::High);
+        val = val.set_cs_pol(Polarity::IdleHigh);
+        assert_eq!(val.cs_pol(), Polarity::IdleHigh);
         assert_eq!(val.0, 0x0000_0004);
-        val = val.set_cs_pol(CsPolarity::Low);
-        assert_eq!(val.cs_pol(), CsPolarity::Low);
+        val = val.set_cs_pol(Polarity::IdleLow);
+        assert_eq!(val.cs_pol(), Polarity::IdleLow);
         assert_eq!(val.0, 0x0000_0000);
 
-        val = val.set_clk_pol(ClockPolarity::High);
-        assert_eq!(val.clk_pol(), ClockPolarity::High);
+        val = val.set_clk_pol(Polarity::IdleHigh);
+        assert_eq!(val.clk_pol(), Polarity::IdleHigh);
         assert_eq!(val.0, 0x0000_0002);
-        val = val.set_clk_pol(ClockPolarity::Low);
-        assert_eq!(val.clk_pol(), ClockPolarity::Low);
+        val = val.set_clk_pol(Polarity::IdleLow);
+        assert_eq!(val.clk_pol(), Polarity::IdleLow);
         assert_eq!(val.0, 0x0000_0000);
 
-        val = val.set_clk_phase(ClockPhase::SecondEdge);
-        assert_eq!(val.clk_phase(), ClockPhase::SecondEdge);
+        val = val.set_clk_pha(Phase::CaptureOnSecondTransition);
+        assert_eq!(val.clk_pha(), Phase::CaptureOnSecondTransition);
         assert_eq!(val.0, 0x0000_0001);
-        val = val.set_clk_phase(ClockPhase::FirstEdge);
-        assert_eq!(val.clk_phase(), ClockPhase::FirstEdge);
+        val = val.set_clk_pha(Phase::CaptureOnFirstTransition);
+        assert_eq!(val.clk_pha(), Phase::CaptureOnFirstTransition);
         assert_eq!(val.0, 0x0000_0000);
     }
 
@@ -2998,11 +2959,11 @@ mod tests {
         assert_eq!(val.bm_cs_ctrl_mode(), BMCsCtrlMode::SpiController);
         assert_eq!(val.0, 0x0000_0000);
 
-        val = val.set_bm_cs_polarity(BMCsPolarity::Low);
-        assert_eq!(val.bm_cs_polarity(), BMCsPolarity::Low);
+        val = val.set_bm_cs_pol(Polarity::IdleHigh);
+        assert_eq!(val.bm_cs_pol(), Polarity::IdleHigh);
         assert_eq!(val.0, 0x0000_0020);
-        val = val.set_bm_cs_polarity(BMCsPolarity::High);
-        assert_eq!(val.bm_cs_polarity(), BMCsPolarity::High);
+        val = val.set_bm_cs_pol(Polarity::IdleLow);
+        assert_eq!(val.bm_cs_pol(), Polarity::IdleLow);
         assert_eq!(val.0, 0x0000_0000);
 
         val = val.set_bm_cs_pin(BMCsPin::Cs0);

artinchip-hal/src/rtc.rs

@@ -0,0 +1,5 @@
+//! Real Time Clock (RTC).
+
+mod register;
+
+pub use register::*;