ScaleSim Accelergy Run Fixes

.gitignore

@@ -25,4 +25,5 @@ test_benchmark*
 result_parser.py
 test*
 configs_test
-benchmark_results
+benchmark_results
+.venv/

README.md

@@ -1,3 +1,5 @@
+## **Please note that this repository is a legacy version for SCALE-Sim v3 and will not have any external updates unless there is a critical bug. Please post your issues/pull requests to the [main repository](https://github.com/scalesim-project/SCALE-Sim).** ##
+
 # Systolic CNN AcceLErator Simulator (SCALE Sim) v3
 
 <!-- [![Documentation Status](https://readthedocs.org/projects/scale-sim-project/badge/?version=latest)](https://scale-sim-project.readthedocs.io/en/latest/?badge=latest) -->
@@ -210,4 +212,3 @@ Advisors
 * Ananda Samajdar
 * Tushar Krishna
 
-

configs/google.cfg

@@ -33,5 +33,5 @@ BlockSize : 8
 RandomNumberGeneratorSeed : 40
 
 [run_presets]
-InterfaceBandwidth: USER
 UseRamulatorTrace: False
+InterfaceBandwidth: CALC

configs/scale.cfg

@@ -36,3 +36,7 @@ RandomNumberGeneratorSeed : 40
 [run_presets]
 InterfaceBandwidth: CALC
 UseRamulatorTrace: False
+SRAM_row_size: 2
+SRAM_bank_size: 5
+DRAM_row_size: 2
+DRAM_bank_size: 5

configs/tpuv5e_downscale.cfg

@@ -24,4 +24,4 @@ FilterSRAMBankNum: 32
 FilterSRAMBankPort: 1
 
 [run_presets]
-InterfaceBandwidth: USER 
+InterfaceBandwidth: USER

requirements.txt

@@ -7,3 +7,4 @@ pandas
 cython
 setuptools
 matplotlib
+tk

rundir-accelergy/accelergy_input/components/XY_NoC.yaml

@@ -0,0 +1,75 @@
+compound_components:
+  version: 0.3
+  classes:
+  - name: XY_NoC
+    attributes:
+      technology: 40nm
+      Y_comparator_width: 4  # compare rowID
+      X_comparator_width: 4  # compare colID
+      n_PE_rows: 12
+      n_PE_cols: 14
+      total_PEs: n_PE_cols * n_PE_rows
+      datawidth: 64
+      Y_X_wire_avg_length: 2mm
+    subcomponents:
+      - name: Y_memory_controller[0..n_PE_rows-1]
+        class: comparator
+        attributes:
+          technology: technology
+          datawidth: Y_comparator_width
+      - name: X_memory_controller[0..total_PEs-1]
+        class: comparator
+        attributes:
+          technology: technology
+          datawidth: X_comparator_width
+      - name: Y_X_wire
+        class: wire
+        attributes:
+          technology: technology
+          width: datawidth + X_comparator_width
+          length: Y_X_wire_avg_length
+    actions:
+      - name: transfer_random
+        arguments:
+          n_rows: 1..n_PE_rows
+          n_cols_per_row: 1..n_PE_cols
+        subcomponents:
+          - name: Y_memory_controller[0..n_rows-1]
+            actions:
+              - name: transfer_random
+          - name: X_memory_controller[0]
+            actions:
+              - name: transfer_random
+                repeat: n_cols_per_row * n_rows # alternative representation of repetitive actions of identical components
+          - name: Y_X_wire
+            actions:
+            - name: transfer_random
+
+      - name: transfer_repeated
+        arguments:
+          n_rows: 1..n_PE_rows
+          n_cols_per_row: 1..n_PE_cols
+        subcomponents:
+          - name: Y_memory_controller[0..n_rows-1]
+            actions:
+              - name: transfer_repeated
+          - name: X_memory_controller[0]
+            actions:
+              - name: transfer_repeated
+                repeat: n_cols_per_row * n_rows
+          - name: Y_X_wire
+            actions:
+            - name: idle
+
+
+      - name: idle
+        subcomponents:
+          - name: Y_memory_controller[0..n_PE_rows-1]
+            actions:
+              - name: idle
+          - name: X_memory_controller[0..total_PEs-1]
+            actions:
+              - name: idle
+          - name: Y_X_wire
+            actions:
+              - name: idle

rundir-accelergy/accelergy_input/components/buffet.yaml

@@ -0,0 +1,117 @@
+compound_components:
+  version: 0.3
+  classes:
+  - name: buffet
+    attributes:
+      technology: 40nm
+      depth: 12
+      width: 16
+      scoreboard_depth: 12
+      address_width: log(depth)
+    subcomponents:
+      - name: scoreboard
+        class: regfile
+        attributes:
+          technology: technology
+          depth: scoreboard_depth
+          width: 1
+      - name: data_fifos[0..2]
+        class: FIFO
+        attributes:
+          technology: technology
+          datawidth: width
+          width: width
+          depth: depth
+      - name: addr_fifos[0..2]
+        class: FIFO
+        attributes:
+          technology: technology
+          datawidth: address_width
+          width: width
+          depth: depth
+    actions:
+      - name: fill
+        arguments:
+          address_delta: 0..1
+          data_delta: 0..1
+        subcomponents:
+          - name: scoreboard
+            actions:
+              - name: access
+                arguments:
+                  address_delta: 1
+                  data_delta: 1
+                  action_latency_cycles: 1
+          - name: data_fifos[0]
+            actions:
+              - name: access
+                arguments:
+                  action_latency_cycles: 1
+          - name: addr_fifos[0]
+            actions:
+              - name: access
+                arguments:
+                  action_latency_cycles: 1
+      - name: read
+        arguments:
+          address_delta: 0..1
+          data_delta: 0..1
+        subcomponents:
+          - name: scoreboard
+            actions:
+              - name: access
+                arguments:
+                  address_delta: 0
+                  data_delta: 0  # 1 bit flag not related to actual data
+          - name: data_fifos[0]
+            actions:
+              - name: access
+                arguments:
+                  action_latency_cycles: 1
+          - name: addr_fifos[0]
+            actions:
+              - name: access
+                arguments:
+                  action_latency_cycles: 1
+      - name: update
+        arguments:
+          address_delta: 0..1
+          data_delta: 0..1
+        subcomponents:
+          - name: scoreboard
+            actions:
+              - name: access
+                arguments:
+                  address_delta: 1
+                  data_delta: 1
+                  action_latency_cycles: 1
+          - name: data_fifos[0]
+            actions:
+              - name: access
+                arguments:
+                  action_latency_cycles: 1
+          - name: addr_fifos[0]
+            actions:
+              - name: access
+                arguments:
+                  action_latency_cycles: 1
+
+      - name: idle
+        subcomponents:
+          - name: scoreboard
+            actions:
+              - name: leak
+                arguments:
+                  action_latency_cycles: 1
+                  data_delta: 0
+                  address_delta: 0
+          - name: data_fifos[0..2]
+            actions:
+              - name: leak
+                arguments:
+                  action_latency_cycles: 1
+          - name: addr_fifos[0..2]
+            actions:
+              - name: leak
+                arguments:
+                  action_latency_cycles: 1

rundir-accelergy/accelergy_input/components/buffet_collection_RF.yaml

@@ -0,0 +1,95 @@
+compound_components:
+  version: 0.3
+  classes:
+  - name: buffet_collection_RF
+    attributes:
+      technology: 40nm
+      memory_depth: 12
+      memory_width: 16
+      n_rdwr_ports: 2
+      n_banks: 1
+      n_buffets: 1
+      scoreboard_depth: 12
+    subcomponents:
+      - name: buffet[0..n_buffets-1]
+        class: buffet
+        attributes:
+          technology: technology
+          depth: memory_depth
+          width: memory_width
+          scoreboard_depth: scoreboard_depth
+      - name: storage
+        class: regfile
+        attributes:
+          technology: technology
+          width: memory_width
+          depth: memory_depth
+          n_rdwr_ports: n_rdwr_ports
+          n_banks: n_banks
+    actions:
+      - name: fill
+        arguments:
+          data_delta: 0..1
+          address_delta: 0..n_banks
+        subcomponents:
+          - name: buffet[0]
+            actions:
+              - name: fill
+                arguments:
+                  address_delta: round(address_delta/n_banks)
+                  data_delta: data_delta
+          - name: storage
+            actions:
+              - name: access
+                arguments:
+                  data_delta: data_delta
+                  address_delta: address_delta
+                  action_latency_cycles: 1
+      - name: read
+        arguments:
+          data_delta: 0..1
+          address_delta: 0..n_banks
+        subcomponents:
+          - name: buffet[0]
+            actions:
+              - name: read
+                arguments:
+                  address_delta: round(address_delta/n_banks)
+                  data_delta: data_delta
+          - name: storage
+            actions:
+              - name: access
+                arguments:
+                  data_delta: data_delta
+                  address_delta: address_delta
+                  action_latency_cycles: 1
+      - name: update
+        arguments:
+          data_delta: 0..1
+          address_delta: 0..n_banks
+        subcomponents:
+          - name: buffet[0]
+            actions:
+              - name: update
+                arguments:
+                  address_delta: round(address_delta/n_banks)
+                  data_delta: data_delta
+          - name: storage
+            actions:
+              - name: access
+                arguments:
+                  data_delta: data_delta
+                  address_delta: address_delta
+                  action_latency_cycles: 1
+      - name: idle
+        subcomponents:
+          - name: buffet[0..n_buffets-1]
+            actions:
+              - name: idle
+          - name: storage
+            actions:
+              - name: leak
+                arguments:
+                  data_delta: 0
+                  address_delta: 0
+                  action_latency_cycles: 1