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fix: introduce 1 cycle latency in Frontend brCommit Self-hosted Difftest #426: Commit 1ae79b4 pushed by CSharperMantle
7m 14s perf-final
perf-final
7m 14s
Revert "fix: int will not care excp" Self-hosted Difftest #425: Commit 6197056 pushed by yizishun
1m 33s perf-final
perf-final
1m 33s
fix: introduce 1 cycle latency in Frontend brCommit Self-hosted Difftest #424: Commit 1ae79b4 pushed by CSharperMantle
15m 10s perf-final
perf-final
15m 10s
fix(lsu): deadlock workaround Self-hosted Difftest #423: Commit 3d3b451 pushed by woshiluo
1m 16s perf-final
perf-final
1m 16s
fix: make frontend branchInfo write-first Self-hosted Difftest #422: Commit 9f936f5 pushed by CSharperMantle
4m 58s perf-final
perf-final
4m 58s
fix: int will not care excp Self-hosted Difftest #421: Commit 8af0b30 pushed by yizishun
6m 14s perf-final
perf-final
6m 14s
fix: int will not care excp Self-hosted Difftest #420: Commit 41ed1d8 pushed by yizishun
55s perf-final
perf-final
55s
fix: fix plbp significant predicate Self-hosted Difftest #419: Commit 9045c6d pushed by CSharperMantle
1m 12s perf-final
perf-final
1m 12s
fix: fix plbp recovery fire conditions Self-hosted Difftest #418: Commit fc738e9 pushed by CSharperMantle
1m 16s perf-final
perf-final
1m 16s
chore: fix typo Self-hosted Difftest #417: Commit dc5d06e pushed by CSharperMantle
1m 46s perf-final
perf-final
1m 46s
fix: correctly use random index when TLBFILL Self-hosted Difftest #416: Commit 15c6737 pushed by CSharperMantle
4m 53s perf-final
perf-final
4m 53s
refactor: use ramdom to choose tlbfill entry Self-hosted Difftest #415: Commit 8a96365 pushed by yizishun
5m 32s perf-final
perf-final
5m 32s
fix: use csr and mmu value Self-hosted Difftest #414: Commit a5386e6 pushed by yizishun
6m 17s perf-final
perf-final
6m 17s
fix: difftest estat Self-hosted Difftest #413: Commit eabae34 pushed by yizishun
6m 16s perf-final
perf-final
6m 16s
fix: fix compile error Self-hosted Difftest #412: Commit e9ac3c7 pushed by yizishun
1m 18s perf-final
perf-final
1m 18s
fix: fix some type error Self-hosted Difftest #411: Commit 249a500 pushed by yizishun
5m 55s perf-final
perf-final
5m 55s
test: add csrEstate and tlbIndex difftest Self-hosted Difftest #410: Commit b6d53b9 pushed by yizishun
1m 19s perf-final
perf-final
1m 19s
ci: patch TLB entries on the fly to match NEMU Self-hosted Difftest #409: Commit a0a3757 pushed by CSharperMantle
1m 14s perf-final
perf-final
1m 14s
fix: add init to frontend and backend pipline reg Self-hosted Difftest #408: Commit efd697e pushed by yizishun
1m 8s perf-final
perf-final
1m 8s
chore: use Undef to randomize input to cacheInfo Self-hosted Difftest #407: Commit 97fbc90 pushed by CSharperMantle
4m 22s perf-final
perf-final
4m 22s
fix: cacheinfo should be 0 when hasCache is 0 Self-hosted Difftest #406: Commit 34b4309 pushed by yizishun
1m 6s perf-final
perf-final
1m 6s
test: tune verilator flags Self-hosted Difftest #405: Commit 6e9c5c6 pushed by CSharperMantle
3m 10s perf-final
perf-final
3m 10s
fix: remove cacheinfo Self-hosted Difftest #404: Commit 397bc27 pushed by yizishun
1m 14s perf-final
perf-final
1m 14s
chore(lsu): init self Self-hosted Difftest #403: Commit ce49c0b pushed by woshiluo
1m 12s perf-final
perf-final
1m 12s
fix: cacheinfo num to 8 Self-hosted Difftest #402: Commit 0b16c8b pushed by yizishun
1m 15s perf-final
perf-final
1m 15s