[3D] Added Basic Test and Fixed Bugs in 3D Flow - #3234
Merged
amin1377 merged 4 commits intoAug 20, 2025
Conversation
While I was experimenting with the 3D flow, I ran into some simple issues in the placement code for a basic 3D FPGA. The issue is that this FPGA has all of the IO tiles on one die and all the CLBs on another. The code was not handling the case when no tile exists on a given die and was hitting assertions and seg faults. I have fixed these issues and added a basic test to exercise this on a set of basic circuits.
github-actions
Bot
added
VPR
amin1377
requested changes
Aug 18, 2025
Contributor
Author
|
@amin1377 Thank you for the review! Please let me know if you have any further comments. |
amin1377
approved these changes
Aug 20, 2025
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
While I was experimenting with the 3D flow, I ran into some simple issues in the placement code for a basic 3D FPGA. The issue is that this FPGA has all of the IO tiles on one die and all the CLBs on another. The code was not handling the case when no tile exists on a given die and was hitting assertions and seg faults.
I have fixed these issues and added a basic test to exercise this on a set of basic circuits.