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Merged
amin1377 merged 4 commits into from
Aug 20, 2025
Merged

[3D] Added Basic Test and Fixed Bugs in 3D Flow #3234

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c8f9d78
[3D] Added Basic Test and Fixed Bugs in 3D Flow
AlexandreSinger Aug 12, 2025
0266d78
Merge remote-tracking branch 'origin/master' into feature-3d-basic-test
AlexandreSinger Aug 19, 2025
e98abf9
[3D] Cleaned Up Checking for Open Positions
AlexandreSinger Aug 19, 2025
0f9cee5
Merge branch 'master' into feature-3d-basic-test
AlexandreSinger Aug 19, 2025
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12 changes: 10 additions & 2 deletions vpr/src/place/compressed_grid.h
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Original file line number Diff line number Diff line change
Expand Up @@ -121,11 +121,17 @@ struct t_compressed_block_grid {
* Useful when the point is of a different block type from coords.
*
* @param grid_loc non-compressed physical tile location in the grid
* @return Nearest x and y compressed locations in the grid (in the same layer)
* @return Nearest x and y compressed locations in the grid (in the same layer),
* or OPEN if a location does not exist.
*/
inline t_physical_tile_loc grid_loc_to_compressed_loc_approx(t_physical_tile_loc grid_loc) const {
auto find_closest_compressed_point = [](int loc, const std::vector<int>& compressed_grid_dim) -> int {
VTR_ASSERT_DEBUG(compressed_grid_dim.size() > 0);
// If the compressed grid dim's size is 0, this means that there are
// no compatible locations for a block of the given type. Returns OPEN
// in that case.
if (compressed_grid_dim.size() == 0) {
return OPEN;
}

// Find the first element not less than loc
auto itr = std::lower_bound(compressed_grid_dim.begin(), compressed_grid_dim.end(), loc);
Expand Down Expand Up @@ -162,6 +168,8 @@ struct t_compressed_block_grid {
}

inline const vtr::flat_map2<int, t_physical_tile_loc>& get_column_block_map(int cx, int layer_num) const {
VTR_ASSERT_SAFE(layer_num < (int)grid.size());
VTR_ASSERT_SAFE(cx < (int)grid[layer_num].size());
return grid[layer_num][cx];
}

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8 changes: 7 additions & 1 deletion vpr/src/place/initial_placement.cpp
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Expand Up @@ -421,12 +421,18 @@ static bool find_centroid_neighbor(ClusterBlockId block_id,
centroid_loc,
num_layers);

// If no compressed location can be found on this layer, return false.
// TODO: Maybe search in the layers above or below.
const t_physical_tile_loc& compressed_loc_on_layer = compressed_centroid_loc[centroid_loc.layer];
if (compressed_loc_on_layer.x == OPEN && compressed_loc_on_layer.y == OPEN && compressed_loc_on_layer.layer_num == OPEN)
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return false;

//range limit (rlim) set a limit for the neighbor search in the centroid placement
//the neighbor location should be within the defined range to calculated centroid location
int first_rlim = rlim;

auto search_range = get_compressed_grid_target_search_range(compressed_block_grid,
compressed_centroid_loc[centroid_loc_layer_num],
compressed_loc_on_layer,
first_rlim);

int delta_cx = search_range.xmax - search_range.xmin;
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10 changes: 8 additions & 2 deletions vpr/src/place/move_utils.cpp
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Expand Up @@ -852,6 +852,12 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type,
centroid,
num_layers);

// If no compressed location can be found on this layer, return false.
// TODO: Maybe search in the layers above or below.
const t_physical_tile_loc& compressed_loc_on_layer = centroid_compressed_loc[to_layer_num];
if (compressed_loc_on_layer.x == OPEN && compressed_loc_on_layer.y == OPEN && compressed_loc_on_layer.layer_num == OPEN)
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return false;

//Determine the valid compressed grid location ranges
int delta_cx;
t_bb search_range;
Expand All @@ -860,12 +866,12 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type,
// If not --> search around the current location of the block but in the direction of the center location that the move proposed
if (range_limiters.original_rlim > 0.15 * range_limiters.first_rlim) {
search_range = get_compressed_grid_target_search_range(compressed_block_grid,
centroid_compressed_loc[to_layer_num],
compressed_loc_on_layer,
std::min<float>(range_limiters.original_rlim, range_limiters.dm_rlim));
} else {
search_range = get_compressed_grid_bounded_search_range(compressed_block_grid,
from_compressed_loc[to_layer_num],
centroid_compressed_loc[to_layer_num],
compressed_loc_on_layer,
std::min<float>(range_limiters.original_rlim, range_limiters.dm_rlim));
}
delta_cx = search_range.xmax - search_range.xmin;
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40 changes: 40 additions & 0 deletions vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d/config/config.txt
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@@ -0,0 +1,40 @@
##############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/blif/4

# Path to directory of architectures to use
archs_dir=arch/multi_die/simple_arch

# Add architectures to list to sweep
arch_list_add=3d_k4_N4_90nm.xml

# Add circuits to list to sweep
# This is a sweep of blif files which pack to a density between 50% and 90% of
# the max density on this device.
circuit_list_add=s820.blif
circuit_list_add=s838.1.blif
circuit_list_add=bw.blif
circuit_list_add=rd84.blif
circuit_list_add=s832.blif
circuit_list_add=mm9a.blif
circuit_list_add=alu2.blif
circuit_list_add=x1.blif
circuit_list_add=t481.blif
circuit_list_add=mm9b.blif
circuit_list_add=styr.blif
circuit_list_add=s953.blif

# Parse info and how to parse
parse_file=vpr_fixed_chan_width.txt

# How to parse QoR info
qor_parse_file=qor_fixed_chan_width.txt

# Pass requirements
pass_requirements_file=pass_requirements_fixed_chan_width.txt

script_params=-starting_stage vpr -track_memory_usage --device FPGA3D --route_chan_width 100

13 changes: 13 additions & 0 deletions vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d/config/golden_results.txt
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@@ -0,0 +1,13 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
3d_k4_N4_90nm.xml s820.blif common 0.42 vpr 60.47 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 34 19 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 61920 19 19 142 161 1 97 72 10 10 200 -1 FPGA3D 21.0 MiB 0.02 962.95 697 2307 262 1349 696 60.5 MiB 0.02 0.00 3.88362 2.8354 -44.0801 -2.8354 2.8354 0.00 0.000264943 0.000221333 0.00564977 0.00487564 -1 -1 -1 -1 799 8.32292 799 8.32292 501 1506 428838 181426 142676 75796.9 975514. 4877.57 11 30528 128848 -1 3.08962 3.08962 -49.9197 -3.08962 0 0 0.17 -1 -1 60.5 MiB 0.08 0.0151992 0.0133702 60.5 MiB -1 0.02
3d_k4_N4_90nm.xml s838.1.blif common 0.38 vpr 60.17 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 31 35 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 61612 35 1 162 163 1 108 67 10 10 200 -1 FPGA3D 20.6 MiB 0.02 971.993 595 2243 199 1309 735 60.2 MiB 0.02 0.00 6.15112 4.77394 -95.0162 -4.77394 4.77394 0.00 0.000272413 0.000234825 0.00560089 0.00486201 -1 -1 -1 -1 663 6.19626 663 6.19626 405 811 187494 70244 142676 69108.9 975514. 4877.57 7 30528 128848 -1 5.22886 5.22886 -100.319 -5.22886 0 0 0.17 -1 -1 60.2 MiB 0.03 0.0126663 0.0112521 60.2 MiB -1 0.02
3d_k4_N4_90nm.xml bw.blif common 0.42 vpr 60.40 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 37 5 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 61848 5 28 137 165 0 95 70 10 10 200 -1 FPGA3D 20.9 MiB 0.02 1001.19 648 2230 233 1237 760 60.4 MiB 0.01 0.00 4.71408 2.68843 -57.8465 -2.68843 nan 0.00 0.000268224 0.000218249 0.00534525 0.00457776 -1 -1 -1 -1 707 7.44211 707 7.44211 423 1074 384187 202338 142676 82484.8 975514. 4877.57 11 30528 128848 -1 2.96576 nan -65.5196 -2.96576 0 0 0.17 -1 -1 60.4 MiB 0.08 0.0156092 0.0137376 60.4 MiB -1 0.02
3d_k4_N4_90nm.xml rd84.blif common 0.44 vpr 60.93 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 48 8 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 62396 8 4 165 169 0 122 60 10 10 200 -1 FPGA3D 21.5 MiB 0.03 1276.53 893 2400 297 1719 384 60.9 MiB 0.02 0.00 5.85628 3.81257 -12.2309 -3.81257 nan 0.00 0.000300758 0.000251555 0.00776715 0.00665884 -1 -1 -1 -1 1137 9.31967 1137 9.31967 626 1981 435438 155572 142676 107007 975514. 4877.57 11 30528 128848 -1 4.35772 nan -13.7036 -4.35772 0 0 0.17 -1 -1 60.9 MiB 0.07 0.0192856 0.016975 60.9 MiB -1 0.02
3d_k4_N4_90nm.xml s832.blif common 0.44 vpr 60.75 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 40 19 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 62212 19 19 167 186 1 115 78 10 10 200 -1 FPGA3D 21.3 MiB 0.02 1154.25 853 2568 290 1474 804 60.8 MiB 0.02 0.00 4.13247 3.10523 -46.8077 -3.10523 3.10523 0.00 0.000290656 0.000240572 0.00583915 0.00503941 -1 -1 -1 -1 969 8.50000 969 8.50000 556 1630 497967 214438 142676 89172.8 975514. 4877.57 11 30528 128848 -1 3.19678 3.19678 -51.7432 -3.19678 0 0 0.17 -1 -1 60.8 MiB 0.09 0.0168909 0.0149564 60.8 MiB -1 0.02
3d_k4_N4_90nm.xml mm9a.blif common 0.43 vpr 60.86 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 43 13 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 62324 13 9 182 191 1 116 65 10 10 200 -1 FPGA3D 21.3 MiB 0.03 1114.43 798 2145 211 1490 444 60.9 MiB 0.02 0.00 10.8478 8.51799 -153.922 -8.51799 8.51799 0.00 0.000330342 0.000283284 0.00706341 0.00611807 -1 -1 -1 -1 932 8.10435 932 8.10435 603 1932 352657 129388 142676 95860.8 975514. 4877.57 12 30528 128848 -1 8.93326 8.93326 -162.518 -8.93326 0 0 0.18 -1 -1 60.9 MiB 0.06 0.0194579 0.0172028 60.9 MiB -1 0.02
3d_k4_N4_90nm.xml alu2.blif common 0.51 vpr 60.84 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 10 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 62304 10 6 207 213 0 147 75 10 10 200 -1 FPGA3D 21.0 MiB 0.03 1523.56 1127 2919 334 2002 583 60.8 MiB 0.03 0.00 8.06149 5.8692 -19.0141 -5.8692 nan 0.00 0.000378537 0.0003192 0.00880031 0.00759421 -1 -1 -1 -1 1501 10.2109 1501 10.2109 1134 4040 723861 248233 142676 131530 975514. 4877.57 20 30528 128848 -1 6.80916 nan -21.7628 -6.80916 0 0 0.17 -1 -1 60.8 MiB 0.13 0.0291658 0.0256409 60.8 MiB -1 0.02
3d_k4_N4_90nm.xml x1.blif common 0.52 vpr 60.36 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 40 51 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 61808 51 35 187 222 0 146 126 10 10 200 -1 FPGA3D 20.8 MiB 0.02 1610.1 1120 4851 495 2050 2306 60.4 MiB 0.02 0.00 4.10122 2.22386 -52.2594 -2.22386 nan 0.00 0.000313872 0.000263201 0.00617901 0.00534275 -1 -1 -1 -1 1195 8.18493 1195 8.18493 758 2273 993709 462977 142676 89172.8 975514. 4877.57 13 30528 128848 -1 2.73628 nan -63.6532 -2.73628 0 0 0.18 -1 -1 60.4 MiB 0.16 0.0192386 0.0170539 60.4 MiB -1 0.02
3d_k4_N4_90nm.xml t481.blif common 0.63 vpr 61.23 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 16 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 62696 16 1 230 231 0 164 72 10 10 200 -1 FPGA3D 21.6 MiB 0.08 1751.01 1378 2307 302 1634 371 61.2 MiB 0.02 0.00 6.37172 4.69357 -4.69357 -4.69357 nan 0.00 0.000397666 0.000329402 0.00835468 0.00715444 -1 -1 -1 -1 1944 11.8537 1944 11.8537 1191 4528 1207016 439295 142676 122613 975514. 4877.57 14 30528 128848 -1 5.09546 nan -5.09546 -5.09546 0 0 0.18 -1 -1 61.2 MiB 0.19 0.0261673 0.0230867 61.2 MiB -1 0.02
3d_k4_N4_90nm.xml mm9b.blif common 0.56 vpr 60.79 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 13 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 62248 13 9 243 252 1 172 85 10 10 200 -1 FPGA3D 21.8 MiB 0.07 1743.55 1331 3805 375 2813 617 60.8 MiB 0.04 0.00 13.0351 10.1648 -199.659 -10.1648 10.1648 0.00 0.000436703 0.000372743 0.0111593 0.00965937 -1 -1 -1 -1 1636 9.56725 1636 9.56725 942 3029 708288 255724 142676 140447 975514. 4877.57 12 30528 128848 -1 11.1431 11.1431 -217.858 -11.1431 0 0 0.17 -1 -1 60.8 MiB 0.12 0.0283152 0.0251122 60.8 MiB -1 0.02
3d_k4_N4_90nm.xml styr.blif common 0.56 vpr 61.01 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 10 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 62476 10 10 253 263 1 148 80 10 10 200 -1 FPGA3D 21.9 MiB 0.08 1496.19 1173 3520 497 2457 566 61.0 MiB 0.03 0.00 4.76272 3.13098 -39.3518 -3.13098 3.13098 0.00 0.000421698 0.000346815 0.0111438 0.00946829 -1 -1 -1 -1 1536 10.4490 1536 10.4490 750 2741 664115 243059 142676 133759 975514. 4877.57 11 30528 128848 -1 3.44654 3.44654 -43.355 -3.44654 0 0 0.18 -1 -1 61.0 MiB 0.11 0.0277392 0.024428 61.0 MiB -1 0.02
3d_k4_N4_90nm.xml s953.blif common 0.60 vpr 61.39 MiB -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 17 -1 -1 success v8.0.0-13571-g061413bc7-dirty release VTR_ASSERT_LEVEL=3 GNU 13.3.0 on Linux-6.8.0-63-generic x86_64 2025-08-12T15:02:26 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_3d 62868 17 23 260 283 1 175 103 10 10 200 -1 FPGA3D 21.8 MiB 0.04 1841.7 1395 4923 669 2986 1268 61.4 MiB 0.04 0.00 4.71306 3.02635 -80.475 -3.02635 3.02635 0.00 0.00045287 0.000379182 0.0114804 0.00980107 -1 -1 -1 -1 1768 10.1609 1768 10.1609 1013 3569 1123409 434789 142676 140447 975514. 4877.57 13 30528 128848 -1 3.2145 3.2145 -87.5477 -3.2145 0 0 0.18 -1 -1 61.4 MiB 0.18 0.0305878 0.0268825 61.4 MiB -1 0.02
1 change: 1 addition & 0 deletions vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt
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@@ -1,4 +1,5 @@
regression_tests/vtr_reg_strong/basic_ap
regression_tests/vtr_reg_strong/basic_3d
regression_tests/vtr_reg_strong/strong_ap/mcnc
regression_tests/vtr_reg_strong/strong_ap/vtr_chain
regression_tests/vtr_reg_strong/strong_ap/bipartitioning_partial_legalizer
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